Plasma-enhanced deposition is commonly utilized during semiconductor fabrication for formation of various compositions. One type of plasma-enhanced deposition is high density plasma chemical vapor deposition (HDP-CVD). The plasma density utilized in an HDP-CVD process contains at least about 1011 free electrons per cubic centimeter. Other plasma-enhanced deposition processes exist besides HDP-CVD, and the invention described herein can have application not only to HDP-CVD processes, but also to other plasma-enhanced deposition processes.
FIG. 1 illustrates an exemplary conventional apparatus 10 which can be utilized in a plasma-enhanced deposition process. Apparatus 10 includes a reaction chamber 12 comprising a sidewall 14. An inlet port 16 extends through sidewall 14, and an outlet port 18 extends across a bottom periphery of the shown chamber construction. Outlet port 18 has a valve 20 thereunder, and typically a pump would be provided to pull material from within chamber 12 when valve 20 is opened. Another valve (not shown) would typically be associated with inlet port 16 to enable the inlet port to be closed during various operations associated with chamber 12.
A wafer holder 22 is shown within chamber 12. Wafer holder 22 would typically be supported by various structures (not shown) to retain the holder in a desired location within chamber 12.
A semiconductor wafer substrate 24 is illustrated supported by wafer holder (chuck) 22. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A plurality of coils 26 are shown extending around an upper region of chamber 12. In operation, coils 26 are utilized to provide energy for maintaining a plasma within chamber 12. Such plasma is illustrated diagrammatically as a cloud 28 in the illustration of FIG. 1. Plasma 28 can be maintained through either inductive coupling or capacitive coupling relative to coils 26.
Power sources 30 and 32 are shown coupled with coils 26 and wafer holder 22, respectively. Power sources 30 and 32 can be utilized to provide power (such as, for example, radiofrequency power) to one or both of the inductive coils and the wafer holder. Although two power sources are illustrated, it is to be understood that a single power source can be utilized for providing power to both the coils and the substrate holder. In a deposition process, the power provided to holder 22 will be utilized to bias substrate 24 relative to plasma 28 so that species from the plasma will be drawn toward the substrate.
In a typical deposition process, one or more precursors are flowed through inlet 16 and utilized to form the deposit ultimately provided over a surface of substrate 24. The precursors can comprise numerous materials, depending on the deposit that is ultimately desired to be formed. For instance, if the deposit is desired to comprise silicon dioxide, the precursors can include a source of silicon and a source of oxygen. The silicon source can, for example, comprise silane; and the oxygen source can, for example, comprise one or more of hydrogen peroxide, diatomic oxygen, and ozone. Alternatively, the silicon source can comprise tetraethylorthosilicate (TEOS).
As another example, if the deposit is to comprise silicon nitride and/or silicon oxynitride, precursors comprising silicon and one or more of nitrogen and oxygen can be flowed into the chamber. A suitable precursor of silicon is silane, and suitable precursors for one or both of oxygen and nitrogen include N2O, NH3, N2, O2.
A carrier gas can be provided to aid in flow of the precursors into chamber 12, as well as to aid in maintaining plasma 28. The carrier gas can comprise, for example, one or more of argon, helium and nitrogen.
FIG. 2 shows an expanded region of an upper left corner of reaction chamber 12 after a deposition process has commenced. A film 40 has formed along an internal surface of sidewall 14. Film 40 is a by-product of the formation of a deposit within chamber 12, and can comprise the same composition as the deposit formed on substrate 24 (FIG. 1), or a different composition. The composition of film 40 includes materials from the precursors flowed into the reaction chamber. Accordingly, if the precursors comprise one or more of silane, oxygen and nitrogen, film 40 will typically comprise, consist essentially of, or consist of one or more of silicon, oxygen and nitrogen.
Material can flake from the film and fall onto a substrate (24 of FIG. 1) within the reaction chamber to form particles across the substrate. The particles can cause numerous problems. For instance, the particles can be detrimental to chemical-mechanical polishing processes in that the particles can gouge a surface during the chemical-mechanical polishing. Also, the particles can be buried in subsequent process steps following a deposition process, and disrupt devices formed over the particles. Further, the particles can interfere with photolithographic processing.
Since particles resulting from flaking of material 40 are problematic, numerous procedures have been developed for removing material 40 from an internal sidewall of reaction chamber 14. Such processes typically comprise cleaning an internal surface of the reaction chamber after a wafer is processed within the chamber.
An exemplary prior art process for depositing material on a wafer surface and cleaning a reaction chamber is described with reference to FIG. 3. Initially, a wafer is placed within the reaction chamber. A deposit is then formed over the wafer surface, and the wafer is subsequently removed from the reaction chamber. After the wafer has been removed from the reaction chamber, interior sidewalls of the chamber are cleaned (typically a dry clean), and then the process can be repeated to treat another wafer. Accordingly, in typical prior art processes a single wafer is processed prior to cleaning internal sidewalls of a reaction chamber. It is noted that some chambers are configured to process a batch of two or more wafers. In such processes, material is deposited over the batch of wafers, and the batch is subsequently removed from the wafer prior to cleaning interior sidewalls of the chamber. In any event, typical prior art processes comprise providing a set of one or more wafers within a reaction chamber, forming a deposit over the set of wafers, and then cleaning interior sidewalls of the chamber before another set of wafers is-processed.
The processing described above is typical for so-called cold wall chambers. Another type of chamber design is a so-called hot wall chamber. Hot wall chambers can have an internal periphery of a sidewall at a higher temperature than treated substrates, and such can reduce a rate of formation of a film along an internal periphery of the chamber relative to the rate of deposition of a material on a substrate. Accordingly, the time between cleanings of the chamber internal sidewalls can be extended and it is not uncommon for hot wall chambers to be cleaned after 3 or 4 batches of wafers, rather than after every batch of wafers.
Regardless of what type of chamber is utilized for forming deposits over wafers (i.e., regardless of whether the chamber is a hot wall or a cold wall chamber), it would be desirable to extend the number of wafers that can be processed by the chamber between cleanings. Extending the number of wafers that can be processed between cleanings can improve wafer throughput, and accordingly can improve the economy of utilizing a chamber.
As discussed previously, an exemplary utilization of deposition methodologies is formation of shallow trench isolation regions. A process of forming shallow trench isolation regions is described with reference to FIGS. 4-6.
Referring initially to FIG. 4, a fragment of a semiconductor wafer construction 50 is illustrated. Construction 50 comprises a semiconductive material mass 52. Mass 52 can comprise, consist essentially of, or consist of, for example, monocrystalline silicon. A series of trenches 54 have been formed to extend into mass 52.
Referring to FIG. 5, an insulative material 56 is deposited over mass 52 and within trenches 54. Material 56 can comprise, consist essentially of, or consist of, for example, silicon dioxide, or silicon dioxide doped with one or both of phosphorus and fluorine. Material 56 can be formed by high density plasma enhanced deposition methodologies.
Material 56 comprises a plurality of peaks 58 and valleys 60, as deposited. The peaks 58 are relatively sharp, which is typical of silicon dioxide formed utilizing a high density plasma deposition process.
FIG. 6 illustrates construction 50 after it has been subjected to a planarization process, such as, for example, a chemical-mechanical polishing process. Such process removes peaks 58 (FIG. 5). The planarization also reduces an uppermost elevation of material 56 to form a planarized upper surface 62 extending across material 56 and an upper surface of mass 52. The material 56 remaining within trenches 54 defines trenched isolation regions. If the trenches are relatively shallow, the isolation regions can be referred to as shallow trench isolation regions.
Methodology of the present invention is described herein which can be utilized for treating a film on an internal periphery of a reaction chamber surface to extend a time between cleanings of the reaction chamber. Such methodology can have application to cold-wall reaction chamber deposition processes and hot-wall reaction chamber deposition processes. In particular aspects, the methodology can have application to processes utilized in the formation of trenched isolation regions.